Differential input stage for electronic equipment, comprising means for reducing interference caused by a voltage or current in common mode

ABSTRACT

According to the invention, means for reducing the interference caused by a voltage or a current in common mode, comprise adders (S 3 ; S 4 ) in each path for adding a first counter-reaction voltage (V 1 ) to the voltage of the relevant path, a bridge (R 1 , R 2 ) and an inverter (I 3 ) for provision of said first counter-reaction voltage which is equal to half the sum of the voltages (VA, VB), respectively supplied to the inputs (A; B), with an opposing sign. According to the invention, the effect of a delay introduced by the inverter (I 3 ) may be reduced, whereby said stage further comprises means (S 5 ; S 6 ) for adding in addition to the input voltage for each path, a second counter-reaction voltage (Va 1 ; Vb 1 ), and means (R 1 , R 2 , I 1 , S 1 ; I 2 , S 2 ) for provision of a second counter-reaction voltage (Va 1 ; Vb 1 ) which is a function of the input voltage (VA; VB) at the input corresponding to said path, with an opposing sign and with a delay identical to that generated by the inverter (I 3 ).

The invention relates to a differential input stage of electronicequipment comprising means for reducing the interference caused by avoltage or a current applied in common mode to two inputs of the stage.It relates in particular to subscriber cards used in telephone exchangesand subscriber terminals. A subscriber card is connected to the terminalof a subscriber by a line comprising at least two conductors used totransmit voice or data signals in both directions and a DC voltageproviding a remote power feed to the terminal. These signals aretransmitted in differential mode, i.e. in the form of a voltagedifference between the two conductors.

The electronic circuits of a subscriber card or a subscriber terminalare subject to interference caused by unwanted signals applied in commonmode. This common mode interference takes the form of voltages andcurrents of equal value on the two conductors of the subscriber line.These voltages and currents have multiple causes. The proximity ofmedium-voltage or high-voltage power lines and switching on the overheadpower cables of electric trains when a train passes may be cited. Moregenerally, any electrical equipment that induces an electrical currentin the subscriber lines creates common mode voltages and currents in theline.

If a subscriber card or terminal is sensitive to common mode voltagesand currents, interference is added to the wanted differential signaland may therefore degrade the transmission of the wanted signal. Theproblem is particularly serious in the case of digital telephoneconnections because the interference may seriously degrade or eveninterrupt the call. To guard against such interference, protection meansare provided at the exchange, on the subscriber cards, and at thesubscriber end, in the terminals.

To reduce such interference, it is conventional to use a transformer andan inductor on a subscriber card. The inductor significantly attenuatesthe transmission of interference caused by common mode voltages andcurrents to the remote power feed generator. The transformer blocks theDC component of the remote power feed current and significantlyattenuates the transmission of interference caused by common modevoltages and currents to the electronic circuits that process the voiceand data signals. Thanks to the transformer, the attenuation of commonmode interference easily reaches 60 dB. A device of this kind has thebulk and weight drawbacks associated with the use of magnetic circuits,ruling out any prospect of integrating the components.

U.S. Pat. No. 4,612,417 describes a differential output stage for asubscriber card adapted to be used in a telephone exchange, where it isconnected to a subscriber line. This differential output stage comprisesmeans for reducing interference caused by a voltage or current appliedin common mode to the subscriber line. It comprises two channels eachconnecting one input of this stage to one output of this stage. Toreduce interference, it comprises on each channel means for adding tothe input voltage of the channel concerned a feedback voltage and meansfor providing this feedback voltage, which is equal to half the sum ofthe voltages present at the respective outputs, with the opposite sign.The interference is completely neutralized if the feedback voltage isexactly equal and opposite to half the sum of the voltages present atthe respective outputs. In practice, the inverter used to invert thesign of this voltage caused some phase delay, which compromises theeffectiveness of the feedback.

The object of the invention is to propose a highly effectivedifferential input stage for reducing common mode interference withoutusing transformers or inductors.

The invention consists in a differential input stage of electronicequipment, comprising means for reducing the interference caused by avoltage or current applied in common mode to two inputs of this stage;this stage comprising two channels each connecting one input to oneoutput; each channel comprising first means for reducing interference,these first means comprising means for adding to the input voltage ofthe channel concerned a first feedback voltage, and means for supplyinga first feedback voltage that is equal to half the sum of the voltagespresent at the inputs, respectively, with the opposite sign;

characterized in that, to reduce the effect of a delay introduced by thecomponents of the means for supplying the first feedback voltage, thisstage further comprises means for further adding to the input voltage ofeach channel a second feedback voltage and means for supplying a secondfeedback voltage that is a function of the voltage at the inputcorresponding to this channel, with the opposite sign, and with a delayidentical to that caused by the components of the means for supplyingthe first feedback voltage.

This stage very effectively reduces common mode interference on eachchannel because the second feedback voltage compensates the effect ofthe delay caused by the components of the means for supplying a firstfeedback voltage.

Another embodiment of the differential stage of the invention furthercomprises, on the upstream side of the first means for reducinginterference, second means for reducing common mode interference,comprising, on each of the channels, means for adding to the inputvoltage of the channel concerned a third feedback voltage, and means forsupplying a third feedback voltage that is equal to k times half the sumof the voltages present at the inputs, respectively, of the differentialstage, with the opposite sign; k being a positive integer less than orequal to 1.

This embodiment reduces electrical power consumption compared to theprevious embodiment because:

-   -   the second means for reducing interference reduce the common        mode voltage applied to the first reduction means (on their        downstream side), so that the first means may receive a supply        voltage that is much lower than in the second embodiment; and    -   the second means for reducing interference do not themselves        lead to any significant increase in consumption because the        means for adding said feedback voltage comprise:        -   two adders that may comprise only passive components, and        -   a single inverter consuming, for the same supply voltage,            less power than the means for providing the second feedback            voltage in the second embodiment (typically comprising three            inverters).            The consumption of this single inverter may be reduced if k            is made significantly less than 1.

The invention will be better understood and other features will becomeapparent with the aid of the following description and the accompanyingdrawings:

-   -   FIG. 1 represents the circuit of one embodiment of a        differential input stage comprising means analogous to those        described in U.S. Pat. No. 4,612,417 for reducing interference        caused by a voltage or current applied in common mode to the        subscriber line.    -   FIG. 2 represents the circuit of a first embodiment of the        differential stage according to the invention offering better        reduction of common mode interference.    -   FIG. 3 represents the circuit of a second embodiment of the        differential stage according to the invention having a much        lower electrical power consumption than the embodiment        represented in FIG. 2.

The embodiment represented in FIG. 1 is intended to be used as asubscriber card input-output stage. It comprises:

-   -   two terminals A and B adapted to be connected to a subscriber        line;    -   two output terminals a and b connected to the inputs of        respective amplifiers AMP2 and AMP3 on the subscriber card;    -   two input terminals c and d connected to the outputs of        respective amplifiers AMP1 and AMP4 on the subscriber card and        connected to the input-output terminals A and B, respectively;    -   a bridge comprising two resistors R1 and R2 of equal resistance        between the terminals A and B;    -   an inverter 13 having an input connected to the mid-point of the        bridge R1R2;    -   an adder S3 having an input connected to the terminals c and A,        an input connected to the output of the inverter I3, and an        output connected to the output terminal a; and    -   an adder S4 having an input connected to the terminals d and B,        an input connected to the output of the inverter I3, and an        output connected to the output terminal b.

Two voltages VA and VB are present at the input-output terminals A andB, respectively:VA=VdA+VmcVB=VdB+Vmc

where:VdA =−VdB

VdA is the voltage of the differential signal at the terminal A,

VdB is the voltage of the differential signal at the terminal B, and

Vmc is the common mode voltage at the terminals A and B.

The mid-point of the bridge R1R2 supplies a voltage (VA+VB)/2 equal tothe voltage Vmc applied in common mode to the subscriber line. If theinverter I3 is a perfect inverter, with no delay between the inputsignal and the output signal, its transfer function is simply −1. Theoutput of the inverter 13 supplies a feedback voltageV1=−(VA+VB)/2=−Vmc.

The adder S3 adds V1 to the input voltage VA to cancel the common modevoltage Vmc. It therefore provides at the output terminal a d voltage:VA=VdA

Similarly, the output of the adder S3 supplies at the output terminal ba voltage:Vb=VdB

The voltage VA of the differential signal supplied to the amplifier AMP2is independent of the common mode voltage Vmc if the components R1, R2,I3 are perfect. The interference consisting of this common mode voltageis therefore eliminated. Likewise, the voltage Vb supplied to theamplifier AMP3. This differential stage therefore cancels interferencecaused by the common mode voltage Vmc.

In reality, an inverter is never perfect and causes a phase delay in theinverted signal. This delay reduces the effectiveness of thecancellation of interference caused by the common mode voltage. Considera non-null delay: the transfer function of the inverter I3 in thefrequency domain becomes −e^(−iφ) where ^(−iφ) represents the phasedelay introduced by the inverter.

In the frequency domain, the equations representing the voltages at theterminals A, B, a, b become:VA=VdA+VmcVB=VdB+VmcV1=Vmc.(1−e ^(−1φ))Va=VdA+V1=VdA+Vmc.(1−e ^(−iφ))Vb=VdB+V1=VdB+Vmc.(1−e ^(−iφ))

These equations show that the voltages VA and VB depend on the commonmode voltage Vmc. Thus cancellation of the interference is incomplete.

FIG. 2 represents the circuit of a first embodiment achieving betterreduction of common mode interference when the inverter I3 is notperfect. This second example includes means identical to the meansconstituting the preceding embodiment, except that the outputs of theadders S3 and S4 are no longer connected directly to the terminals a andb, respectively. It therefore comprises:

-   -   two terminals A and B adapted to be connected to a subscriber        line;    -   two output terminals a and b connected to the inputs of        respective amplifiers AMP2 and AMP3 of the subscriber circuits;    -   two input terminals c and d connected to the outputs of        respective amplifiers AMP1 and AMP4 and connected to the        input-output terminals A and B, respectively;    -   a bridge of two resistors R1 and R2 of equal resistance between        the terminals A and B;    -   an inverter I3 having an input connected to the mid-point of the        bridge R1R2;    -   an adder S3 having an input connected to the terminals c and A,        an input connected to the output of the inverter I3, and an        output a2; and    -   an adder S4 having an input connected to the terminals d and B,        an input connected to the output of the inverter I3, and an        output b2.

It further comprises the following means:

-   -   an inverter I1 having an input connected to the terminals A and        c, and an output;    -   an inverter I2 having an input connected to the terminals B and        d, and an output;    -   an adder S1 having two inputs connected to the mid-point of the        bridge R1R2 and to the output of the inverter I1, respectively,        and an output a1;    -   an adder S2 having two inputs connected to the mid-point of the        bridge R1R2 and to the output of the inverter I2, respectively,        and an output a2;    -   an adder S5 having an inverting input connected to the output a1        of the adder S1, a non-inverting input connected to the output        a2 of the adder S3, and an output connected to the output        terminal a; and    -   an adder S6 having an inverting input connected to the output b1        of the adder S2, a non-inverting input connected to the output        b2 of the adder S4, and an output connected to the output        terminal b.

The inverters I1, I2, I3 have the respective transfer functions:−e^(−1φ1), −e^(−iφ2), −e^(−iφ3)

The improvement to the device consists in further adding to the inputvoltage of each channel a second feedback voltage that neutralizesresidual interference, which voltage is equal to Vmc.(1−e^(−iφ)). Thissecond feedback voltage is obtained in particular by inverting the inputvoltage corresponding to this channel using a second inverter causing adelay identical to that caused by the first inverter I3.

The voltages at the input-output terminals A and B are:VA=VdA+VmcVB=VdB+VmcV1=−Vmc.e ^(−iφ3)

The voltage at the output a1 of the adder S1 is:V a1=−e ^(−iφ1).(VdA+Vmc)+(VA+VB)/2=−VdA.e ^(−iφ1) +Vmc.(1−e ^(iφ1))

The voltage at the output b1 of the adder S2 is:V b1=−e ^(−iφ2).(VdB+Vmc)+(VA+VB)/2=−VdB.e ^(−iφ2) +Vmc.(1+e ^(iφ2))

The voltage at the output a2 of the adder S3 is:V a2=VdA+Vmc−Vmc.e ^(−iφ3) =VdA+Vmc.(1−e ^(−iφ3))

The voltage at the output b2 of the adder S4 is:V b2=VdB+Vmc−Vmc.e ^(−iφ3) VdB+Vmc.(1−e ^(−iφ3))

The voltage at the output a of the adder S5 is:Va=Va2−Va1=VdA.(1+e ^(−iφ1))+Vmc.(e ^(−iφ1) −e ^(−iφ3))

The voltage at the output b of the adder S6 is:Vb=Vb2−Vb1=VdB.(1+e ^(−iφ2))+Vmc.(e ^(−iφ2) −e ^(−iφ3))

As the inverters I1, I2, I3 have the same electric circuit, it ispossible to consider, to a first approximation, that their transferfunctions are all equal to −e^(−iφ). Then:V a≈VdA.(1+e ^(−iφ))≈2 VdAV b≈VdB.(1+e ^(−iφ))≈2 Vd

Note that the voltage Va and the voltage Vb are independent of the valueof the common mode voltage Vmc, even though the delays of the invertersare non-null. Interference caused by the common mode voltage Vmc istherefore eliminated. The same applies to a common mode current. Commonmode voltage and current attenuations of 50 dB have been achieved withthis second embodiment.

FIG. 3 represents the circuit of a second embodiment of the differentialstage according to the invention offering better reduction ofinterference than the embodiment represented in FIG. 1, and much lowerelectrical power consumption than the embodiment represented in FIG. 2.It includes in particular a circuit D2 identical to the embodimentrepresented in FIG. 2 except that the terminals A and B are no longerthe input-output terminals of the differential stage. The input-outputterminals are the terminals A′ and B′ respectively connected to theinput terminals c and d of the differential stage and to an additionalinterference reduction device. This additional device is on the upstreamside of the circuit D2 and has a structure analogous to that of thedifferential stage represented in FIG. 1, to bring about a firstreduction of the common mode voltage. This additional device comprises:

-   -   two terminals A′ and B′ adapted to be connected to a subscriber        line;    -   two output terminals respectively connected to the inputs A and        B of the circuit D2;    -   two input terminals c and d respectively connected to the        outputs of two amplifiers AMP1 and AMP4 on the subscriber card        and respectively connected to the input-output terminals A′ and        B′;    -   a bridge comprising two resistors R1′ and R2′ of equal        resistance between the terminals A′ and B′;    -   an inverter I3′ having an input connected to the mid-point of        the bridge R1′R2′;    -   an adder S3′ having an input connected to the terminals c and        A′, an input connected to the output of the inverter I3′, and an        output connected to the terminal A;    -   an adder S4′ having an input connected to the terminals d and        B′, an input connected to the output of the inverter I3′, and an        output connected to the terminal B.

Two voltages VA′ and VB′ are present at the input-output terminals A′and B′, respectively:VA′=VdA′+VmcVB′=VdB′+Vmc

Where:VdA′=−VdB′

VdA′ is the voltage of the differential signal at the terminal A′,

VdB′ is the voltage of the differential signal at the terminal B′, and

Vmc is the common mode voltage at the terminals A′ and B′.

The mid-point of the bridge R1′R2′ provides a voltage (VA′+VB′)/2 equalto the voltage Vmc applied in common mode to the subscriber line. If theinverter I3′ is a perfect inverter, with no time-delay between the inputsignal and the output signal, its transfer function is simply −1. Theoutput of the switch I3′ supplies a feedback voltageV3=−(VA′+VB′)/2=−Vmc.

The adder S3′ adds V3 to the input voltage VA′ to cancel the common modevoltage Vmc. It therefore supplies at the terminal A a voltage:VA=VdA′

Similarly, the output of the adder S4′ then supplies at the terminal B avoltage:VB=VdB′

The voltage VA of the differential signal supplied to the circuit D2 isindependent of the common mode voltage Vmc, to the degree that thecomponents R1′, R2′, I3′ are perfect. The interference constituted bythis common mode voltage is therefore eliminated (or at least reduced).The same applies to the voltage VB. This additional device thereforeprovides a first reduction of interference caused by the common modevoltage Vmc; however, it additionally enables the circuit D2 to bedesigned so that it consumes less electrical power.

This is because, since the common mode voltage at the terminals A and Bhas been eliminated (or at least greatly reduced), the voltages appliedto the inputs of the inverters I1, I2, I3 are reduced. It is thenpossible to power them at a lower voltage, without risk of saturation.However, the inverter I3′ must be able to operate with a high commonmode voltage. It therefore requires a high supply voltage. Overall thereis a saving in energy since the inverter I3′ is the only one that has tobe supplied at a high voltage, whereas, in the embodiment represented inFIG. 2, three inverters I1, I2, I3 must be supplied at a high voltage.

This second embodiment may be modified to reduce the consumption of theinverter I3′. This modification consists in using an inverter I3′ havinga gain k greater than 0 and less than 1. Then:VA=VdA+Vmc.(1−k)VB=VdB+Vmc.(1−k)

Neutralization of the common mode voltage Vmc by this inverter I3′ istherefore not complete, but will be completed in the next stagecomprising the inverters I1, I2, I3. On the other hand, the inverter I3′then requires a lower supply voltage, which reduces the electrical powerconsumption of the inverter I3′ . The value of k is chosen takingaccount of the amplitude conditions of the common mode voltages andcurrents and the required global power consumption.

1. Differential input stage (1) of electronic equipment, comprisingmeans for reducing the interference caused by a voltage or currentapplied in common mode to two inputs (A; B) of this stage; this stagecomprising two channels each connecting one input (A; B) to one output(a; b); each channel comprising first means for reducing interference,these first means comprising, on each of the channels, means (S3; S4)for adding to the input voltage of the channel concerned a firstfeedback voltage (V1), and means (R1, R2, I3) for supplying a firstfeedback voltage that is equal to half the sum of the voltages (VA; VB)present at the inputs (A; B), respectively, with the opposite sign;characterized in that, to reduce the effect of a delay, introduced bythe components of the means (R1, R2, I3) for supplying the firstfeedback voltage (V1), this stage further comprises means (S5; S6) forfurther adding to the input voltage of each channel a second feedbackvoltage (Va1; Vb1) and means (R1, R2; I1, S1; I2, S2) for supplying asecond feedback voltage (Va1; Vb1) that is a function of the voltage(VA; VB) at the input corresponding to this channel, with the oppositesign, and with a delay identical to that caused by the components of themeans (R1, R2, I3) for supplying the first feedback voltage (V1). 2.Stage according to claim 1, characterized in that it further comprises,on the upstream side of the first means for reducing interference,second means for reducing common mode interference, comprising, on eachof the channels, means (S3′; S4′) for adding to the input voltage of thechannel concerned a third feedback voltage (V3), and means (R1′, R2′,I3′) for supplying a third feedback voltage that is equal to k timeshalf the sum of the voltages (VA′; VB′) present at the inputs (A′; B′),respectively, of the differential stage, with the opposite sign; k beinga positive integer less than or equal to
 1. 3. Stage according to claim2, characterized in that the means (R1′, R2′, I3′) for supplying a thirdfeedback voltage (V3) comprise a bridge of two resistors (R1′, R2′),connected to the inputs (A′, B′) of the differential stage, and aninverter (I3′ ) having an input connected to the mid-point of the bridgeand having an output supplying the third feedback voltage (V3).